1. Field of the Invention
The present invention relates to a voltage-controlled oscillator circuit.
2. Description of the Related Art
Generally, a quartz oscillator circuit is used as a clock pulse source. A quartz oscillator circuit is fundamentally of the resonant oscillation type and so it is difficult to obtain any desired frequency other than the resonant frequency. On the other hand, with a voltage-controlled oscillator circuit, a desired frequency can be easily obtained by adjusting the charging and discharging times of capacitors or capacitive elements. For this reason, a voltage-controlled oscillator circuit is normally used in an apparatus which needs different clock frequencies.
Today, CMOS integrated circuits of low power consumption have become widespread. With this trend, various voltage-controlled oscillator circuits of the CMOS configuration are being developed. Voltage-controlled oscillator circuits of the CMOS configuration are classified into two major categories: single-capacitor type and double-capacitor type.
A typical voltage-controlled oscillator circuit of the single-capacitor type is a ring oscillator type as shown in 17(a). In this configuration, the source and drain currents of a CMOS inverter 151 are controlled, using voltage-controlled current sources 152 and 153, respectively. The charging and discharging times of a capacitive element 154 disposed on the output side of the CMOS inverter 151 are controlled, thus controlling the oscillation frequency variations in the voltage at a terminal 15A of this voltage-controlled oscillator circuit are shown in the waveform diagram of FIG. 17(b). As can be seen from this diagram, when the N-channel MOS transistor of the CMOS inverter 151 turns off and the P-channel MOS transistor turns on, an electric current from the voltage-controlled current source 152 on the side of the source electrically charges the capacitive element 154, thus increasing the voltage at the terminal 15A. This charging time TC is determined by the value of the current from the voltage-controlled current source 152. The voltage at the terminal 15A is reduced when the P-channel MOS transistor of the CMOS inverter 151 turns off and the N-channel MOS transistor turns on, thus discharging the capacitive element 154 via its source and via the voltage-controlled current source 153 on the side of the source. This discharging time TD is determined by the voltage-controlled current source 153 on the side of the source electrode. The period Tc, i.e., the oscillation frequency, is controlled by controlling these charging and discharging times by the voltage-controlled current sources. In FIG. 17(b), Td indicates the delay time introduced by the CMOS inverters 155 and 156. The voltage developed between power supply terminals VDD and VSS is set to 5 V. The threshold voltage of the CMOS inverter 151 is 2.5 V.
A voltage control circuit disclosed in Japanese Patent Laid-Open No. 62215/1984 is one example of the double-capacitor type voltage-controlled oscillator circuit. As shown in FIG. 18(a), this circuit comprises two CMOS inverters 162 and 163 having P-channel MOS transistors whose source electrodes are both connected to a voltage-controlled current source 161. One capacitive element 164 is connected with the output terminal of one CMOS inverter 162. One comparator circuit 165 compares the charging voltage for the capacitive element 164 with a given threshold voltage V.sub.REF. Another capacitive element 166 is connected with the output terminal of the other CMOS inverter 163. Another comparator circuit 167 compares the charging voltage for the capacitive element 166 with the given threshold voltage. The voltage control circuit further includes a flip-flop 168 having a set terminal S connected with the output of one comparator circuit and a reset terminal R connected with the output terminal of the other comparator circuit. The flip-flop 168 further has output terminals Q and Q for producing an output and an inverted output. The output terminal Q is connected with the input terminal of one CMOS inverter 162. The output terminal Q is connected with the input terminal of the other CMOS inverter 163. In this voltage-controlled oscillator circuit, when the output from the flip-flop 168 goes low (L) and the inverted output goes high (H), the N-channel MOS transistor of one CMOS inverter turns off, while the P-channel MOS transistor turns on. As a result, one capacitive element is charged. At the same time, the P-channel MOS transistor of the other CMOS inverter turns off and the N-channel MOS transistor turns on. Hence, the other capacitive element is discharged. The voltages at the various terminals are shown in the waveform diagram of FIG. 18(b). As one capacitive element is charged, the voltage at a terminal 16A increases. When the given threshold voltage V.sub.REF is exceeded, the output from one comparator circuit goes high (H). The flip-flop 168 is set. The output from the flip-flop 168 goes high (H). The inverted output goes low (L). In response to this, one capacitive element 164 starts to be discharged. At the same time, the other capacitive element 166 starts to be charged. As the voltage at a terminal 16B increases and goes beyond the given threshold voltage V.sub.REF, the output from the other comparator circuit 167 goes high (H), thus resetting the flip-flop 168. The inverted output changes from a high (H) state to a low (L) state. As described thus far, in this voltage-controlled oscillator circuit, the two capacitive elements are alternately charged and discharged to produce an oscillation output across the output terminals Q and Q. The oscillation frequency can be controlled by controlling the charging times of the two capacitive elements by means of the voltage-controlled current sources. In FIG. 18(b), TC indicates the charging time. Td indicates the delay time. Tc indicates the period.
The above-described single-capacitor type voltage-controlled oscillator circuit is essentially composed of a ring oscillator consisting of CMOS inverters and hence relatively simple in structure. Although this circuit is capable of operating at low voltages, the charging and discharging times are not uniform because of the difference in performance between the P-channel and N-channel MOS transistors forming the CMOS inverter 151. As a consequence, the duty cycle cannot be well controlled.
In the above-described double-capacitor type voltage-controlled oscillator circuit, the timing at which the flip-flop is set and reset (i.e., the periods for which the flip-flop is at high and low levels, respectively) is determined by the time in which the capacitive elements are charged by the MOS transistors of the same type (in the example shown in FIG. 18(a), the P-channel MOS transistors). Therefore, the duty cycle can be controlled well. However, the logic gate such as a NOR gate forming the flop-flop introduces a large delay. That is, as is well known in the art, the simplest R-S flip-flop comprises a pair of NOR gates No0 and No1, as shown in FIG. 19(a). These NOR gates No0 and No1 have input terminals b0 and b1, respectively, which are connected with output terminals Q and Q of mutually opposite gates. The NOR gates No0 and No1 further have input terminals S and R, respectively, which are a set terminal and a reset terminal, respectively. An equivalent circuit of this circuitry is shown in FIG. 19(b). As can be seen from this figure, a high (H) signal is first applied to the input terminal S. The following sequence of operations is carried out until the output terminal Q goes high (H). The N-channel MOS transistor connected with the input terminal S turns on, thus lowering the voltage at the input terminal b1. In response to this, the NOR gate no1 is inverted. This increases the voltage at the input terminal b0. In response to this, the NOR gate no0 is inverted. This further lowers the voltage at the input terminal b1. Because the plurality of MOS transistors are connected in series between the power supply and the output terminals, the delay introduced by this series of operations is made larger by the capacitive and resistive components associated with the MOS transistors than the delay of the CMOS inverters that are delay elements in the ring oscillator. For this reason, the double-capacitor type voltage-controlled oscillator circuit has the disadvantage that its operation speed is low. Hence, high frequencies cannot be obtained. As can be seen from FIG. 19(b), in the double-capacitor type voltage-controlled oscillator circuit, a large amount of electric current passes through the flip-flop. This makes it difficult to suppress the electric power consumption. In addition, the flip-flop is unsuited for lower power voltage operation, because a plurality of MOS transistors are connected in series between the power supply and the output terminals.